TIA 1A - TELEVISION INTERFACE ADAPTOR (MODEL 1A)
6. Moving Object Graphics Registers
A. General Description
There are five graphics registers for moving objects on
this chip. These graphics registers are loaded (written) in
parallel by the microprocessor and like the playfield
register are scanned and converted to serial output.
Unlike the playfield register, which is always scanned
beginning at the left side of each horizontal line, moving
object graphics registers are scanned only when triggered
by a start decode from their horizontal position counter.
A typical graphics register is shown in figure 4 .
The graphics registers for both missiles are identical and
very simple. They each consist of a one bit register called
missile enable (ENAM0, ENAM1). This graphics bit is scanned
(outputted) only when triggered by its corresponding
position counter. There are control bits (bits 4, 5, of
NUSIZ0, NUSIZ1) that can stretch this single graphics bit
out over widths of 1, 2, 4, or 8 clocks of horizontal line
time. (A full line is 160 clocks).
The graphics registers for both players are identical and
are rather complex. They each consist of eight bit parallel
registers (GRP0, GRP1) and a bi-directional parallel to
serial scan counter that converts the parallel data into
serial output. A one bit control register (REFP0, REFP1)
determines the direction (reflection) of the parallel to
serial scan, outputing either D7 through D0, or D0 though
D7. This allows reflection (horizontal flipping) of player
serial graphics data without having to flip the
microprocessor data.
The clock into the scan counter can be controlled (three
bits of NUSIZ0 and NUSIZ1) to slow the scan rate and
stretch the eight bits of serial graphics out over widths
of 8, 16, or 32 clocks of horizontal line time. These same
control bits are used in the player-missile motion counters
to control multiple copies, so only three player widths (
scan
rates) are available.
Each of the player graphics registers actually consists of
two 8 bit parallel registers. The first (GRP0, GRP1) is
loaded (written) from the microprocessor 8 bit data bus.
The second is automatically loaded from the output of the
first. The reason for this is a complex subject called
vertical delay. A large amount of microprocessor time is
required to generate player, missile and playfield graphics
(table look up, masking, comparisons, etc.) and load these
into this chip's registers. For most game programs this
time is just too large to fit into one horizontal line
time. In fact for most games it will barely fit into two
line times (127 microseconds). Therefore, individual
graphics registers are loaded (written) every two lines,
and used twice for serial output between loads. This type
of programing will obviously limit the vertical height
resolution of objects to multiples of two lines. It also
will limit the resolution of vertical motion to two lines
jumps. Nothing can be done about the vertical height
resolution; however, vertical motion can be resolved to a
single line by addition of a second graphics register that
is automatically parallel loaded from the output of the
first, one line time after the first was loaded from the
data bus. This second graphics register output is
therefore always delayed vertically by one line. A control
bit called vertical delay (VDEL0, VDEL1) selects which of
these two registers is to be used for serial output. If
this control bit is set by the microprocessor between
picture frames, the object will be moved down (delayed) by
one line during the next frame. In most programming
applications player 0 graphics and player 1 graphics are
loaded (written) alternately, during the blank time just
prior to each line as shown in (figure 1). Since GRP0 and
GRP1 addresses from the microprocessor alternate, they are
delayed by one line from each other. The GRP0 address
decode can therefore be used to load the delayed graphics
register for player 1, and GRP1 likewise to load the
delayed graphics register for player 0. The two vertical
delay bits (VDEL0, VDELl) then select delayed or undelayed
registers for player 0 and player 1 as serial outputs.
E. Ball Graphics
The ball graphics register is almost identical to the
missile graphics register. It also consists of a single
enable bit (ENABL) whose output is triggered by the ball
position counter. It also has two control bits (bits 4, 5
of CTRLPF) that can stretch this single graphics bit out
over widths of 1, 2, 4, or 8 clocks of horizontal line
time. Unlike the missile graphics; however, the ball
graphics register has capability for vertical delay similar
to the player graphics. A second graphics (enable) bit is
alternately loaded from the output of the first, one line
after the first was loaded from the data bus. A ball
vertical delay bit (VDELBL) selects which of these two
graphics bits is used for the ball serial output. The first
graphics bit (ENABL) should be loaded during the same
horizontal blank time as player 0 (GRP0), because GRP1 is
used to load the second enable bit from the output of the
first on alternate lines.